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In this paper we present a low-noise, high-frame-rate global shutter CMOS image sensor with UHD resolution (3840 × 2160), targeting high-speed machine vision applications. The sensor (ForzaFAST581) supports video capture at up to 1141 FPS at 12 bits and 1694 FPS at 8 bits at full resolution, consuming a total power of 5.5 W. Fabricated in a 65 nm, four-metal BSI process, the imager features a 5 µm voltage-domain global shutter pixel with dual-gain capability for improved dynamic range and a read noise of 3.04 e− in global shutter and 2.15 e− in rolling shutter mode for high-gain at maximum frame rate operation. For compact camera integration and low power consumption, the sensor is designed to stream video through 16 CML data ports, each operating at 7.44 Gbps, achieving a total aggregate throughput of 119 Gbps. Additionally, the sensor supports selectable output bit depths—8-bit, 10-bit, and 12-bit—allowing frame rate optimization based on application-specific requirements.

We developed a 2.2 µm backside-illuminated (BSI) global shutter (GS) pixel featuring true charge-domain-correlated double sampling (CDS). To enhance the inverse parasitic light sensitivity (1/PLS), we implemented a thick-film epitaxial process incorporating a dual-depth deep trench isolation (DTI) structure. The thickness of the epitaxial substrate was 8.5 µm. This structure was designed using optical simulation. By using a thick epitaxial substrate, it is possible to reduce the amount of light that reaches the memory node. The dual-depth DTI design, with a shallower trench on the readout side, enables efficient signal transfer from the photodiode (PD) to the memory node. To achieve this structure, we developed a process for thick epitaxial substrate, and the dual-depth DTI can be fabricated with a single mask. This pixel represents the smallest charge-domain GS pixel developed to date. Despite its compact size, it achieves a high quantum efficiency (QE) of 83% (monochrome sample: wavelength = 560 nm) and a 1/PLS exceeding 10,000 (white halogen lamp with IR-cut filter). The pixel retains 80% of its peak QE at ±15° incident angles and maintains stable 1/PLS performance even under low F-number (F#) conditions.

This paper describes an ultra-high-speed monolithic global shutter CMOS image sensor capable of continuous motion capture at 326,000 fps with a resolution of 640 × 480 pixels. The performance is enabled by a novel combination of pixel technology and circuit techniques. The highly sensitive BSI pixel with a 52 μm pitch employs a fully depleted substrate to facilitate rapid photocarrier transport. In-pixel voltage mode storage enables pipelined readout, while in-pixel analog CDS provides low noise with minimal impact on readout speed. The sensor achieves an equivalent row time of 6.4 ns through separate top and bottom readout together with multiple parallel ADCs per column. Independent row drivers on both the left and right sides ensure the global shutter accuracy needed for the minimum exposure time of 59 ns. The dynamic range is enhanced by on-chip reduction in FPN and by PTC-based data compression. The sensor delivers a throughput of 100 Gpix/sec, transferred off chip via 128 CML channels operating at 6.6 Gbps each. The device is fabricated using a 130 nm monolithic CIS process with BSI postprocessing and is in series production.

A 10 × 10 µm2 radiation-tolerant voltage-domain global shutter pixel with radiation-hardened by design (RHBD) device modification is developed to operate under high ionizing-dose rates and high total ionizing-dose (TID) levels. Therefore, a modified NMOS transistor layout is used in the pixel to achieve radiation hardness. The pixel design is demonstrated to operate up to 1 MGy or 100 Mrad (SiO2) TID with minimal degradation. The global shutter pixel also includes correlated double sampling (CDS) to reduce noise and the impact of the collected carriers generated by the flux of gamma or X-ray radiation. Combined with an external flash, global shutter operation allows short exposures, which limits the impact of radiation on dark current and dynamic range. The pixel is designed using 180 nm CMOS Image Sensor (CIS) technology.

We present a 1024 × 512, 1000 fps, high-dynamic-range global shutter CMOS image sensor. The pixel is based on a voltage domain global shutter architecture, featuring a pitch of 24 μm × 24 μm. Both high-gain and low-gain signals can be captured within a single frame. The combined dynamic range is 95 dB, and the full well capacity is 620 ke-. In this paper, we analyze the pixel noise performance as well as the non-linearity and image lag that arise from parasitic capacitance in the pixel. The ramp generator is based on a 12-bit full thermometer code current-steering DAC with high driving capability. We discuss the design considerations for the ramp generator, particularly addressing the phenomenon of non-linear response. Finally, the comparator design and the column readout noise are analyzed.

A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal–oxide–semiconductor (CMOS) image sensors (APS) with at least four transistors is presented. This model, based on the fundamental principles of electronic noise, may provide a reliable calibration of the gain conversion, which is one of the most important parameters of CMOS Image Sensor pixels. The new model revisits the “gold standard” ratio method of the measured variance of the shot noise to the mean value. The model assumes that shot noise is the dominant noise source of the pixel. The microscopic random time-dependent voltage of any shot noise electron charging the junction capacitance C of the sensing node may have either an exponential form or a step form. In the former case, a factor of 1/2 appears in the variance to the mean value, namely, q/2C is obtained. In the latter case, the well-established ratio q/C remains, where q is the electron charge. This correction factor affects the parameters that are based on the conversion gain, such as quantum efficiency and noise. The model has been successfully tested for advanced image sensors with six transistors fabricated in a commercial FAB, applying a CMOS 180 nm technology node with four metals. The stochastic modeling is corroborated by measurements of the quantum efficiency and simulations with advanced software (Lumerical).

We introduce a compact voltage-domain global shutter CMOS image sensor for a wide range of applications including consumer, IoT, and industrial applications. With 0.5 MP and 2.79 µm pixels packed in a die size of only 2.3 mm × 2.8 mm, the sensor achieves more than 92% quantum efficiency (QE) in the visible wavelength and more than 36% at near-infrared (940 nm) all while drawing a mere 20 mW at a 10-bit, 30-frame-per-second operational mode. In this article, we focus on the architecture of the sensor and the design challenges encountered to fit all the necessary circuitry in such a limited footprint. Moreover, we detail the new solutions we have developed to meet the demanding specifications of low-power operation and high dynamic range (HDR).

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

We developed a new 2.5 μm global shutter (GS) pixel using a 65 nm process with an advanced light pipe (LP) structure. This is the world’s smallest charge domain GS pixel reported so far. This new developed pixel platform is a key enabler for ultra-high resolution sensors, industrial cameras with wide aperture lenses, and low form factors optical modules for mobile applications. The 2.5 μm GS pixel showed excellent optical performances: 68% quantum efficiency (QE) at 530 nm, ±12.5 degrees angular response (AR), and quite low parasitic light sensitivity (PLS)—10,400 1/PLS with the F#2.8 lens. In addition, we achieved an extremely low memory node (MN) dark current 13 e−/s at 60 °C by fully pinned MN. Furthermore, we studied how the LP technology contributes to the improvement of the modulation transfer function (MTF) in near infrared (NIR) enhanced GS pixel. The 2.8 μm GS pixel using a p-substrate showed 109 lp/mm MTF@50% at 940 nm, which is 1.6 times better than that without an LP. The MTF can be more enhanced by the combination of the LP and the deep photodiode (PD) electrically isolated from the substrate. We demonstrated the advantage of using LP technology and our advanced stacked deep photodiode (SDP) technology together. This unique combination showed an improvement of more than 100% in NIR QE while maintaining an MTF that is close to the theoretical Nyquist limit (MTF @50% = 156 lp/mm).