Explore the vast range of titles available.

This letter presents a fully integrated 22‐MHz relaxation oscillator for ultra‐low‐power applications in automotive internet‐of‐things (IoT) systems. Fabricated using a 110‐nm CMOS process, the oscillator occupies an active area of 0.05 mm2 ${\\rm mm}^2$ . Empowered by the complementary input comparator featuring power efficiency and low propagation delay, the oscillator achieved an extremely low‐power consumption of 5.9 μW $\\mu {\\rm W}$from a 1‐V power supply, resulting in an unprecedented energy efficiency of 0.27 μW/MHz $\\mu \\text{W/MHz}$ , enabling continuous operation for up to 58 years on a standard LR6 dry battery. The periodic jitter is 131 ps and the start‐up time is within 1.2 μs $\\mu {\\rm s}$ . It operates across a wide temperature range from −40∘C $^{\\circ }{\\rm C}$to 160∘C $^{\\circ }{\\rm C}$ . Micrograph of the proposed ultra‐low‐power relaxation oscillator chip, which consumes 5.9 μW $\\mu {\\rm W}$from a 1‐V supply at 22 MHz output, achieving an unprecedented energy efficiency of 0.27 μW/MHz $\\mu \\text{W/MHz}$ .

A low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency. This letter demonstrates a 1‐to‐3 GHz fast‐locking and low‐power SPLL fabricated in 28 nm CMOS. The proposed adaptive fast‐locking scheme maintains a reduced settling time with tiny power and area overhead. Moreover, a start‐up module is adopted to further reduce loop latency and increase system robustness. The measured RMS jitter and peak‐to‐peak jitter are 2.33 ps and 17.00 ps, respectively. Therefore, this proposed SPLL is an effective solution for various wireline standards. For example, in USB 3.0 (5Gbps) standard, total jitter budget of the transmitter is 75 ps.

This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply. This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 μW from a 1.5‐V supply.

High step‐down DC‐DC converters require a robust and low power pre‐regulated supply for bandgap reference. This paper proposes a structure that comprised of two current paths to achieve energy efficient pre‐regulation under high and low input voltage conditions. The design eliminated large size resistors for current limiting which is usually required for high input supplies. The presented pre‐regulator structure combined with the bandgap circuit was realized with the TSMC 180‐nm BCD process. The measured results show the proposed structure has a wide input voltage range of 3.5–45 V, a temperature coefficient of 5.63 ppm/°C and typical average current consumption of 1.1 μA. This paper proposed a dual‐channel pre‐regulation structure for the bandgaps, which is suitable for the high step‐down DC‐DC convertors with low quiescent current and small area requirement.

An ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1‐kb SRAM prototype based on the single‐ended cells with built‐in self‐test (BIST) and power‐delay production (PDP) reduction circuits was realised on silicon using 40‐nm CMOS technology. Theoretical derivations and simulations of all‐PVT‐corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock. This work demonstrates an ultra low power SRAM on silicon, which is featured with single‐ended cells, supply voltage selection circuit for each memory column, and a PDP reduction circuit. The measurement result shows that it attains a record low 1.0 fJ energy per bit.

Low power consumption has become an essential criterion in the development of next‐generation electronics, driven by the growing adoption of Internet of Things, wearables, and portable platforms. Oxide semiconductor thin‐film transistors (TFTs) have become most promising candidates for next‐generation low‐power electronics due to their wide band‐gap, low leakage current, high mobility, steep subthreshold swing, and compatibility with low‐temperature flexible processing. In this review, recent advances in the use of oxide TFTs for low‐power electronics are systematically summarized. First, the inherent advantages of oxide semiconductor materials over other commonly used materials (e.g., amorphous hydrogenated silicon, low temperature polycrystalline silicon, organic semiconductors, etc.) for realizing low power consumption are demonstrated. Then, strategies to reduce power consumption are further discussed, including interface engineering, such as the novel source‐gated transistors, and structural engineering, such as dual‐gate and underlap designs. Finally, a comprehensive review of oxide TFTs for various low‐power electronics applications, including logic circuits, active‐matrix arrays, flexible electronics, monolithic 3D integration, and neuromorphic computing, is presented, demonstrating their great potential in future low‐power and flexible electronic systems. This review explores the progress of oxide semiconductor thin‐film transistors in low‐power electronics. It illustrates the inherent material advantages of oxide semiconductor, which enable it to meet the low‐power requirements. It also discusses current strategies for reducing power consumption, including interface and structure engineering. Finally, it illustrates their applications in logic circuits, active‐matrix arrays, flexible electronics, 3D integration, and computing.

A true‐time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non‐idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor‐less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non‐idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S11 and S22 parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. This paper surveys the Process variations, ageing effects, field variations, and other non‐idealities of the true‐time delay (TTD) cell devices. The body bias technique is presented and applied to the wideband CMOS inductor‐less TTD cell. With this technique, the threshold voltage can be manipulated intentionally and any variation in this voltage can be compensated.

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static‐to‐dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state‐of‐the‐art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS‐like, SDCVSL, and pseudo N‐type, respectively, in terms of energy consumption.

Abstract This letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle. The sensor effectively tackles the weak pull‐up challenge inherent in DLS logic ensuring its compatibility with standard digital logic. By capitalizing on the super cut‐off attribute of DLS logic, the frontend of the sensor achieves ultra‐low power consumption, without compromising on measurement precision or the breadth of the temperature range. The digital part of the proposed utilizes the output frequency of the sensor's frontend as the clock source, in conjunction with an external 50 Hz reference clock, achieving a low overall power consumption. The frontend of the temperature sensor was fabricated using a 180 nm process, occupying a minimal area of 374 μm2. The digital part of the circuit is implemented using FPGA. Following a two‐point calibration and system error removal, the sensor, operating at a supply voltage of 0.8 V, demonstrated a 3δ error of ±0.54 ∘C across the temperature range of −20 to 125 ∘C. At 25 ∘C, the resolution figure of merit of the sensor was 0.037 pJ K2, with a maximum voltage sensitivity of 4.2 ∘C/V.