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The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi-user (MU) multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) technique is adopted for the high data rate communication. In an MIMO-OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight-parallel multimode (N = 512/256/128/64) multi-path delay commutator-based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU-MIMO-OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre-, post-FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre-transformed data reordering and 11.64 mW for the post-transformed data reordering with an area occupation of 0.7694 mm2 and 0.5111 mm2, respectively.