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Quaternary logic can be implemented using quantum dot gate-quantum dot channel field effect transistors (QDG-QDCFETs) which produce four states in their transfer characteristics. A circuit model is used to simulate a four-state state inverter which is the basic building block of any multi-valued logic (MVL) circuit design. A basic problem of MVL implementation is the noise margin. The stable nature of the transfer characteristics of the QDG-QDCFET can make them a promising circuit element in future MVL circuit design. Comparison of fabricated device characteristics and the model data is shown.

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. This paper conducts a survey of the existing logic families for ternary adders. It tried to address and clarify some problematic issues existing in the previous papers as well as provide statistical and technical information about design strategies utilised in the literature.

This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

Multiple-channel field-effect transistors (MCFETs) switch the current among different channels in the FET based on the applied voltage in its gate terminal. MCFETs can be used to design a multivalued logic circuit with the lowest number of circuit elements. Different MCFET logic circuits and unipolar inverters are now considered to be an option to follow Moore’s law. However, many details about the performance of MCFET in different logic circuit applications are in the research phase. In this paper, a circuit model of MCFET based on Verilog-A has been developed and a circuit for multivalued dynamic random-access memory (DRAM) is designed.

Ternary circuits are promising due to their lower interconnect complexity, storage requirement, and lesser pin count than binary circuits. The adder is one of the most important building blocks of a digital processor. This paper proposes carbon nanotube field effect transistor (CNTFET)-based ‘exact’ and ‘approximate’ ternary full adders (TFA). The CNTFET is attractive for realizing multi-valued logic (MVL)/ternary circuits because its threshold voltage can be changed by altering the diameter of its carbon nanotube (CNT). The exact ternary adders are realized using unary functions and multiplexers. The circuit size of only the ‘Sum’ block of a TFA is pruned in approximate ternary full adders by varying degrees for achieving superior performance in terms of transistor count, delay, and power consumption compared to the ‘exact’ TFAs. This performance gain in approximate TFAs is obtained at the cost of accuracy in some of the ‘Sum’ outputs. Circuits are simulated with HSPICE using a 32 nm CNTFET technology node at various supply voltages and temperatures. The proposed exact adders exhibit lower power consumption and transistor count, higher robustness, and lower power delay product (PDP) and energy delay product (EDP) than existing ternary adders. The improvement in PDP of the proposed exact TFAs varies from 20 to 96% compared to existing TFAs. The performance of the exact TFAs is then further improved by approximating its ‘Sum’ block in approximate TFAs. Image blending is used to demonstrate the effectiveness of approximate ternary adders in error-tolerant applications.

Negative differential resistance (NDR), a peculiar electrical property in which current decreases with increasing voltage, is highly desirable for multivalued logic gates, memory devices, and oscillators. Recently, 2D quantum-tunneling NDR devices have attracted considerable attention because of the inherent atomically flat and dangling-bond-free surfaces of 2D materials. However, the low current density of 2D NDR devices limits their operating frequency to less than 2 MHz. In this study, graphene/hexagonal boron nitride (h-BN)/graphene resonant tunneling transistors (RTTs) were fabricated using graphene and h-BN barriers with different numbers of atomic layers, showing a mechanism enabling the observation of NDR in high current density devices. A triangular etching approach was proposed to suppress the effects of graphene–metal contact resistance and graphene sheet resistance, enabling pronounced NDR effect even in a 2D tunneling device with a single atomic layer h-BN barrier. A room-temperature peak current density up to 2700 μA/μm 2 and operational frequencies up to 11 GHz were achieved, demonstrating the potential of 2D quantum NDR devices for applications in high-speed electronics. 2D devices with negative differential resistance are desired for multivalued logic applications, but they are normally limited by low current densities and operational frequency. Here, the authors report graphene/hexagonal boron nitride/graphene resonant tunnelling transistors with room temperature peak current density up to 2700 μA/μm 2 and operational frequencies up to 11 GHz.

The design of a three-input logic circuit using carbon nanotube field effect transistors (CNTFETs) is presented. Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices, which is why this design is so popular, and it also reduces chip area, both of which are examples of circuit overheads. The proposed module we have investigated is a triple-logic-based one, based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values, as well as comparisons of the design working with various load capacitances. Comparing the proposed design with the existing design, the delay times was reduced from 66.32 to 16.41 ps, i.e., a 75.26% reduction. However, the power dissipation was not optimized, and increased by 1.44% compared to the existing adder. The number of transistors was also reduced, and the product of power and delay (P*D) achieved a value of 0.0498053 fJ. An improvement at 1 V was also achieved. A load capacitance (fF) was measured at different values, and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps, with a range of 61.06 ps. The power dissipations ranged from a minimum of 3.38 µW to a maximum of 6.49 µW. Based on these results, the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

The advancement of emerging technologies favors the proliferation of multi-valued logic design as it offers enhancement of circuit performance parameters with increased level of integration. This work has presented carbon nanotube field effect transistor (CNTFET) based ternary shift register designs which are realized by employing single-edge triggered ternary D-flip-flop cells with reset input. The dependency of threshold voltage on carbon nanotube physical dimensions is used for the realization of multiple threshold voltages in ternary logic designs. The D-flip flop design with reset capability implementation is performed using multiplexer based positive and negative latches arranged in master–slave architecture. Further, the D-flip-flop cells with reset input are combined to construct Ternary logic serial input serial output (SISO), parallel input parallel output (PIPO) and parallel input serial output (PISO) registers. The latching of the input across the output happens only if the reset input is high otherwise no latching is performed. The PISO register is operating in two modes of loading and shifting realized using NAND logic. The proposed ternary shift register designs using CNTFETs are simulated using HSPICE considering the 32 nm Stanford CNTFET model. The results demonstrate that for 4-bit register design, power and PDP improvements of more than 70% are achieved for SISO designs and a maximum of 90% is attained for PIPO and PISO register designs as compared to recent counterparts. The Monte-Carlo simulation results indicate robust and stable operation of the proposed designs when subjected to process variations.

Carbon nanotube field effect transistor (CNTFET) based multivalued logic (MVL) circuits capable of delivering high computational efficiency are required in contemporary digital systems for resolving data transfer issues. Quaternary logic can lead to the reduction of interconnections, as more information can be transferred by using four logic levels in high-speed and high-density. This work proposes novel standard quaternary inverter, SQNAND and SQNOR logic gates based on the stacking technique. These novel gates have been used in the design of a quaternary half adder. The simulation results for proposed quaternary circuits have been obtained using HSPICE with the 32 nm CNTFET Stanford model. The proposed designs of SQI, SQNAND, and SQNOR circuits are operated at a supply voltage of 0.9 V and show power delay product (PDP) of 0.776, 1.523, and 2.746 aJ, respectively. The area consumed by SQI, SQNAND, and SQNOR circuits is 7636, 16,456, 16,864 λ2, respectively. Further, the power consumption and PDP for the proposed QHA are 1.01 µW and 0.806 10–16 J, respectively. The proposed QHA shows improvement in PDP in contrast to other QHA designs reported earlier and is anticipated to be used for futuristic computing systems.

In this communication, a new semiconductor optical amplifier (SOA)-based module for multi-valued logic units using the cross-polarization modulation effect is proposed and analyzed. The design is simple and compact, consisting of only three SOAs and a few passive optical elements. SOAs have very low switching power (< 1mW), and are very small (< 1 mm) and integrable into modern optical integrated circuits. Being multifunctional, the design is versatile; it can function as a demultiplexer, comparator, half adder, half subtractor, and as basic (OR, AND), universal (NOR, NAND), XOR, and XNOR logic gates. This design follows a tree architecture, operates at very high speed (~ 100Gbit/s), and provides a good Q factor (30 dB or more). The corresponding bit error rate (BER) is very low (~ 10 –24 ). In this work, a relative eye opening as large as 90.4% is calculated. The variations in Q and BER with noise and control power are also investigated.