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The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

A floating FDNR using four OTAs (operational transconductance amplifiers) and two grounded capacitances have been reported in this article. As per the reviewed literature, the proposed floating FDNR is based upon a minimum number of transistors with a resistor-less and grounded capacitances based structure as compared to any other FDNR simulators and can be considered the most compact configuration ever reported. It offers some excellent features like; electronically tunable behavior, purely resistor-less architecture, no restraint of parameter values matching, use of only grounded capacitances, and fully symmetric floating architecture. We have investigated the circuit for port parasitics and non-ideal gains of the employed OTAs and presented the analysis. It is found that the circuit nature remains almost unchanged in non-ideal conditions. The influence of frequency-dependent transconductance has also been analyzed. The FDNR simulation through the reported circuit has been verified through the PSPICE-generated simulation results. The higher-order CDR filtering circuit application of the proposed FDNR has also been reported and checked through simulations. The presented OTA-based FDNR has been experimentally verified through the CA3080 IC-based implementation and results are discussed.

This paper presents a new operational transconductance amplifier (OTA) design for batteryless biomedical front-ends. The proposed OTA operates in the subthreshold region and utilizes self-cascode devices to achieve ultra-low power, low noise, and a high common-mode rejection ratio (CMRR). Post-layout simulations in Cadence, using 45 nm CMOS technology with 0.9 V supply voltage, show a power consumption of 49.3 nW, a CMRR of 144.9 dB, an input-referred noise of 4.51 μVrms integrated over 0.5–208 Hz, and a noise efficiency factor of 1.023 with a core silicon area of 0.00138 mm2. Using the proposed OTA, we implemented a 10-channel neural recording amplifier for Local Field Potentials (LFPs) based on a capacitively coupled, capacitive-feedback (CC-CF) topology with a body-driven pseudo-resistor high-pass path. The system achieves a total CMRR ≥ 70 dB and an estimated power of 494.2 nW for 10 channels. Compared with prior art, the proposed OTA offers competitive noise efficiency and common-mode rejection at lower power, making it a viable building block for batteryless neural and biomedical sensing front-ends.

Parallel-type slew-rate enhancers (PSREs) improve the driving capability of operational transconductance amplifiers (OTAs) for large capacitive loads. While capacitive-boosting (CB) techniques enhance PSRE efficiency in fully-differential designs, their application to single-ended configurations—common in off-chip load driving—remains unexplored. This work identifies a critical limitation of standard CB in single-ended unity-gain buffers: severe slew-rate degradation due to large common-mode input swings. To overcome this, we propose a novel split CB (SCB) technique for single-ended PSREs that strategically divides the boosting capacitance. Simulated in a 0.18-µm CMOS process, the proposed method achieves a ×5.53 reduction in settling time compared to standard CB when driving a 1-nF load. With only 4 µA quiescent current under a 3.3-V supply, it attains a 1% settling time of 2.56 µs for 2.64-V steps, demonstrating robust performance across process-voltage-temperature variations. This technique enables low-power, high-speed interfaces for drivers of off-chip devices.

This paper presents a high-efficiency, nW-level operational transconductance amplifier (OTA) capable of operating at 0.3 V with rail-to-rail input and output. The design utilizes a bulk-driven technique in the input stage to extend the common-mode input range under ultra-low-voltage conditions. A simplified intermediate stage ensures reliable MOS operation at ultra-low-voltage levels while reducing power consumption, and a modified Class-AB controlled output stage facilitates rail-to-rail output and enhances current efficiency. Fabricated using SMIC 0.18 μm technology and operating at a 0.3 V supply, the OTA achieves a DC gain of 63.07 dB, phase margin of 61.5°, a gain-bandwidth product of 37.68 kHz, and a slew rate of 21.85 V/ms while consuming only 123 nW with a 60 pF load. The design also demonstrates superior small-signal figures of merit (12.25 MHz·pF/μW) and large-signal figures of merit (10.66 V/μs·pF/μW) compared to state-of-the-art low-voltage OTAs. These results indicate that the proposed amplifier offers a balanced solution of low power consumption, wide bandwidth, and high slew rate, making it well-suited for energy-constrained applications such as portable electronics, IoT sensors, and biomedical devices.

This paper presents an ultra-low-voltage high-performance bulk-input pseudo-differential operational transconductance amplifier for low-frequency applications. The proposed amplifier is designed using standard 65-nm CMOS technology and powered from 0.3-V supply with a stand by current consumption of 170-nA. Post-layout simulations with a load capacitance of 5 pF have been performed to validate the performance of the proposed amplifier. The proposed amplifier exhibits a DC gain of 60 dB and a phase margin of 53\\[^\\circ \\] at unity gain frequency of 70 kHz for a load of 5 pF. The proposed OTA has shown improvement of five times and more than 2.5 times in small-signal and large-signal performance, respectively, when compared to the state of the art. In addition, the proposed transconductance amplifier is used to design a tunable second-order \\[G_m{\\text {-}}C\\] low-pass filter. Simulation results show that tunable cutoff frequency is varying from 4 to 190 kHz which is obtained by varying the input-stage bias current from 1 to 200 nA.

This article presents a proficient architecture of a power-efficient gate-driven two-stage fully-differential operational transconductance amplifier (FD-OTA). The proposed fully-differential OTA operating in the subthreshold region offers a more comprehensive input and output voltage range. It exploits forward body-biasing techniques in the current mirror load that is employed on a composite input core. Further, both stages are adaptively biased using two gate-driven cascoded flipped voltage follower (CASFVF) differential amplifiers to eliminate the dedicated tail current sources and operate in super class-AB mode. The overall structure allows precise bias current control across pseudo-differential pairs, leading to low process, voltage, and temperature (PVT) variance in small and large signal performance characteristics. In open-loop operation, the proposed approach allows the 0.35-V operated OTA to obtain a voltage gain of 96.16 dB, a CMRR of 158.68 dB, a phase margin of 65.18°, and a unity gain frequency of 43.73 kHz for a 15 pF capacitive load in UMC 0.18-µm CMOS technology. Moreover, an average slew rate of 5.11 V/µs for a power dissipation of 70 nW establishes the highest large-signal figure-of-merit (FOM L ) among the latest state-of-the-art, proving its usefulness in high-speed applications as well.