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A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate
A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate
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A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate
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A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate
A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate

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A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate
A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate
Journal Article

A 0.35-V cascoded flipped voltage follower assisted improved fully-differential subthreshold gate-driven class-AB OTA with boosted gain, CMRR, and slew rate

2023
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Overview
This article presents a proficient architecture of a power-efficient gate-driven two-stage fully-differential operational transconductance amplifier (FD-OTA). The proposed fully-differential OTA operating in the subthreshold region offers a more comprehensive input and output voltage range. It exploits forward body-biasing techniques in the current mirror load that is employed on a composite input core. Further, both stages are adaptively biased using two gate-driven cascoded flipped voltage follower (CASFVF) differential amplifiers to eliminate the dedicated tail current sources and operate in super class-AB mode. The overall structure allows precise bias current control across pseudo-differential pairs, leading to low process, voltage, and temperature (PVT) variance in small and large signal performance characteristics. In open-loop operation, the proposed approach allows the 0.35-V operated OTA to obtain a voltage gain of 96.16 dB, a CMRR of 158.68 dB, a phase margin of 65.18°, and a unity gain frequency of 43.73 kHz for a 15 pF capacitive load in UMC 0.18-µm CMOS technology. Moreover, an average slew rate of 5.11 V/µs for a power dissipation of 70 nW establishes the highest large-signal figure-of-merit (FOM L ) among the latest state-of-the-art, proving its usefulness in high-speed applications as well.