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Three-dimensional (3D) integrated circuits, which use a vertically stacked design of 2D planar chips in a 3D arrangement using through-silicon-via (TSV) technology have been developed to minimise chip footprint, enable higher integration density, decrease power consumption and reduce fabrication cost. Floorplanning without considering power can increase the number of power TSVs and bumps needed to solve IR drop constraint in 3D power delivery network. In this study, the authors propose a methodology for minimising the power TSVs and bumps based on power-aware floorplanning using specific power patterns to solve IR drop constraint on the 3D power delivery network. The authors’ methodology moves high power-consuming blocks to the dedicated pattern area which is able to minimise the number of power TSVs and bumps while solving the IR drop constraint. The simulation results show that the proposed method can reduce the total number of power TSVs and bumps by 13.7 and 12.2%, respectively, after power-aware floorplanning while solving the IR drop constraint.

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller, modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents ChipletQuake, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, ChipletQuake detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects hardware Trojans and interposer tampering.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

A design space exploration of the countermeasures for hardware masking is proposed in this paper. The assumption of independence among shares used in hardware masking can be violated in practical designs. Recently, the security impact of noise coupling among multiple masking shares has been demonstrated both in practical FPGA implementations and with extensive transistor level simulations. Due to the highly sophisticated interactions in modern VLSI circuits, the interactions among multiple masking shares are quite challenging to model and thus information leakage from one share to another through noise coupling is difficult to mitigate. In this paper, the implications of utilizing on-chip voltage regulators to minimize the coupling among multiple masking shares through a shared power delivery network (PDN) are investigated. Specifically, different voltage regulator configurations where the power is delivered to different shares through various configurations are investigated. The placement of a voltage regulator relative to the masking shares is demonstrated to a have a significant impact on the coupling between masking shares. A PDN consisting of two shares is simulated with an ideal voltage regulator, strong DLDO, normal DLDO, weak DLDO, two DLDOs, and two DLDOs with 180∘ phase shift. An 18 × 18 grid PDN with a normal DLDO is simulated to demonstrate the effect of PDN impedance on security. The security analysis is performed using correlation and t-test analyses where a low correlation between shares can be inferred as security improvement and a t-test value below 4.5 means that the shares have negligible coupling, and thus the proposed method is secure. In certain cases, the proposed techniques achieve up to an 80% reduction in the correlation between masking shares. The PDN with two DLDOs and two-phase DLDO with 180∘ phase shift achieve satisfactory security levels since t-test values remain under 4.5 with 100,000 traces of simulations. The security of the PDN improves if DLDO is placed closer to any one of the masking shares.

Nowadays, almost all electronic systems on printed circuit boards (PCB) adopt a vital element known as the power delivery network (PDN). However, the performance of the PDN is susceptible to variables such as the temperature and aging of its key constituents: the decoupling capacitors (decaps). Consequently, the long-term reliability of the PDN demands meticulous consideration to foresee how its performance can deviate from the initial design specifications. A realistic high-current server system is considered. It involves hundreds of decaps to achieve the required target impedance as optimally selected and laid out by the Power Integrity (PI) designer. The degradation of decap performance is analyzed by collecting experimental data from tens of decaps for each type used in the design while applying an accelerated aging process at different temperatures. The impact of aging in terms of the capacitance, parasitic inductance, and resistance of the decaps is considered to illustrate an innovative methodological design approach based on statistical analysis. Such a design approach can prevent the detrimental impact of a larger noise level due to the gradual performance degradation of the PDN over the intended life cycle of the system.

An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm (GA) and Artificial Neural Network (ANN). The ANN is first trained by an appropriate set of results obtained by a commercial simulator. Once the ANN is ready, it is used within an iterative GA process to place a minimum number of decoupling capacitors for minimizing the differences between the input impedance at one or more location, and the required target impedance. The combined GA–ANN process is shown to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators. With the new approach the accuracy of the results remains at the same level, but the computational time is reduced by at least 30 times. Two test cases have been considered for validating the proposed approach, with the second one also being compared by experimental measurements.

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (ICCmax) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths ICC trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining ICCmax and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning.

This paper presents a hybrid modelling approach that combines physics-based electromigration modelling (PEM) and statistical methods to evaluate the electromigration (EM) limits of nano-interconnects in mesh networks. The approach, which is also compatible with standard Place and Route (P&R) tools and practises, takes into account the positive impact of network redundancy on EM current limits. The numerical simulations conducted in this study show that conventional methods underestimate the EM current limits of a power delivery network (PDN) unit-cell by 80% due to their lack of consideration for redundancy. Additionally, the time-to-failure (TTF) distributions of a PDN unit-cell obtained by the developed modelling framework adhered to a lognormal distribution, where the lognormal sigma, σlogn, exhibits a 55% reduction compared to that of the single constituent interconnects. The study also found the negative voltage (i.e., ground or Vss) grid to be more susceptible to EM than the positive voltage, i.e., Vdd grid. In the examined grid unit-cell design, both the number of interconnect sites prone to voiding and also the magnitude of the peak tensile stress within the nano-interconnects were found to be two times as high in the Vss case compared to Vdd. The lognormal sigma of TFF for the grid unit-cells, σlogn−tile, show a marked reduction compared to the lognormal sigma of the constituent single interconnects, σlogn, with a 50% and 66% decrease compared to single interconnects, for downstream (Vss) and upstream (Vdd), respectively. In addition, σlogn−tile was three times higher for downstream (Vss) compared to upstream (Vdd), whilst, in contrast, this difference was only 2-fold at the single interconnect level. TTF50% was predicted to be 4.13-fold higher at the grid unit-cell level for the upstream compared to downstream operation, which was also more pronounced than in the single interconnect level where the difference was only 2-fold. This research provides valuable insights into the EM ageing of nano-interconnects in mesh networks and could pragmatically enhance the accuracy of EM compliance evaluation methods.

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance (Rth) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD–top-VSS (TDTS), bottom-VDD–bottom-VSS (BDBS), and bottom-VDD–top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The Rth of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the Ion is increased by 2% for NFET and 7% for PFET.