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Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector
Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector
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Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector
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Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector
Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector

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Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector
Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector
Paper

Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector

2019
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Overview
In order to achieve the challenging requirements on the CLIC vertex detector, a range of technology options have been considered in recent years. One prominent idea is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel readout chips. Recent results have shown the approach to be feasible, though more detailed studies of the performance of such devices, including simulation, are required. The CLICdp collaboration has developed a number of ASICs as part of its vertex detector R&D programme, and here we present results on the performance of a CCPDv3 active sensor glued to a CLICpix readout chip. Charge collection characteristics and tracking performance have been measured over the full expected angular range of incident particles using 120 GeV/c secondary hadron beams from the CERN SPS. Single hit efficiencies have been observed above 99% in the full range of track incidence angles, down to shallow angles. The single hit resolution has also been observed to be stable over this range, with a resolution around 6 \\(\\mu\\)m. The measured charge collection characterstics have been compared to simulations carried out using the Sentaurus TCAD finite-element simulation package combined with circuit simulations and parametrisations of the readout chip response. The simulations have also been successfully used to reproduce electric fields, depletion depths and the current-voltage characteristics of the device, and have been further used to make predictions about future device designs.