MbrlCatalogueTitleDetail

Do you wish to reserve the book?
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes
Hey, we have placed the reservation for you!
Hey, we have placed the reservation for you!
By the way, why not check out events that you can attend while you pick your title.
You are currently in the queue to collect this book. You will be notified once it is your turn to collect the book.
Oops! Something went wrong.
Oops! Something went wrong.
Looks like we were not able to place the reservation. Kindly try again later.
Are you sure you want to remove the book from the shelf?
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes
Oops! Something went wrong.
Oops! Something went wrong.
While trying to remove the title from your shelf something went wrong :( Kindly try again later!
Title added to your shelf!
Title added to your shelf!
View what I already have on My Shelf.
Oops! Something went wrong.
Oops! Something went wrong.
While trying to add the title to your shelf something went wrong :( Kindly try again later!
Do you wish to request the book?
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes

Please be aware that the book you have requested cannot be checked out. If you would like to checkout this book, you can reserve another copy
How would you like to get it?
We have requested the book for you! Sorry the robot delivery is not available at the moment
We have requested the book for you!
We have requested the book for you!
Your request is successful and it will be processed during the Library working hours. Please check the status of your request in My Requests.
Oops! Something went wrong.
Oops! Something went wrong.
Looks like we were not able to place your request. Kindly try again later.
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes
Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes
Journal Article

Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes

2023
Request Book From Autostore and Choose the Collection Method
Overview
A dual-gate electrostatically-doped monolayer transition metal dichalcogenide tunneling field-effect transistor (EDTFET) and a chemically-doped monolayer transition metal dichalcogenide tunneling field-effect transistor (CDTFET) have been investigated using non-equilibrium Green function formalism for subdeca nanometer (sub-10 nm) technology nodes. The EDTFET and CDTFET structures are proposed to achieve high performance and low power, and benchmarked with IRDS 2022 projections for 2025, 2028, 2031, and 2034. The EDTFET for VDG=VDS= 0.65 V and VSG=-0.65 V exhibits better performance than IRDS 2022 projections in terms of subthreshold swing (SS) with a value of 43 mV/dec. Moreover, the scalability analysis confirmed that the channel length LCH≥7 nm exhibits comparable ION as per IRDS 2022 projections and other state of the art 2-D material TFETs. A comparison study has been performed between three different doping techniques, EDTFET, CDTFET, and dual metal charge plasma-doped (CPTFET), to choose the doping technique which is suitable for sub-10 nm high-performance technology nodes. The ION, ION/IOFF ratio, and SS for EDTFET were 1385 μA/μm, 1.38×105, and 54 mV/dec, respectively, better than IRDS 2022 predictions, therefore projecting it as a suitable candidate for low-power and high-performance applications. The EDTFET exhibits the highest ION, and comparable ION/IOFF and SS compared to the two alternative doping techniques utilizing 2-D TMD materials at sub-10 nm technology nodes. Finally, a circuit level comparison for low-power and high-performance applications has also been performed for 45 stages of the inverter circuit at subdeca nanometer technology nodes.