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Electrical noise in Ge-source double-gate PNPN tunnel field effect transistor
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Journal Article
Electrical noise in Ge-source double-gate PNPN tunnel field effect transistor
2023
Overview
The noise behavior of a proposed Ge-source counter-doped pocket-based double-gate tunnel FET (GS-PNPN-TFET) in the presence and absence of interfacial trap charge conditions is presented. The noise behavior was studied in terms of drain current noise power spectral density (
S
id
, unit A
2
/Hz) and gate voltage electron noise power spectral density (
S
vg
ee, unit V
2
/Hz) against variation of various device parameters, viz., body thickness (
T
si
), pocket length (
L
p
), gate-oxide thickness (
T
ox
), gate-oxide material, mole fraction, and doping density using Sentaurus TCAD software. Oxide–semiconductor interfacial trap charge of Gaussian distribution was used at two frequencies − 1 MHz and 10 GHz. Our analysis also includes the impact of temperature variation on noise. As per our findings, the noise spectrums are comparable for the presence and absence of interfacial trap charges in the proposed TFET. This is because the noise spectrum depends on on-current (
I
ON
) and the
I
ON
is negligibly influenced by the interfacial trap charges in the proposed TFET. However, off-current (
I
OFF
) degrades when trap charges are present at the interface. In comparison with other FET devices, the proposed device offers improved
S
id
and
S
vg
ee values of roughly 1.82 × 10
–29
A
2
/Hz and 5.5 × 10
–20
V
2
/Hz, respectively, at 10 GHz frequency. Furthermore, the diffusion noise predominates at higher frequencies, while the generation–recombination noise is found to be dominant at low frequencies, as expected. Flicker noise is most noticeable at low and medium frequencies but fades away at higher frequencies.
Publisher
Springer India,Springer Nature B.V
