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Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation
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Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation
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Journal Article
Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation
2023
Overview
The impact of the work function modulation (WFM) in sub-20nm strained silicon channel double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power arithmetic circuit applications. A 14nm double gate junctionless transistor (DGJLT) followed by formation of strained channel and WFM in metal gate is designed on sentaurus TCAD, where 2-D mixed mode simulation at supply voltage (V
D
D
) = 0.8V is performed to configure a hybrid full adder (HFA). From the analyses, the WFM based HFA is found to be superior by providing the least power, delay and PDP. The variability of HFAs is also tested as a function of the physical parameters like V
D
D
, load capacitor, and temperature.
