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Linearity improvement of gain enhanced op-amp using cross-coupled architecture
by
Pandey, Abhishek
, Vishwanathan, Vedam
, Nath, Vijay
, Chakraborty, Subhra
, Prasad, Deepak
in
Electronics and Microelectronics
/ Engineering
/ Instrumentation
/ Mechanical Engineering
/ Nanotechnology
/ Technical Paper
2018
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Linearity improvement of gain enhanced op-amp using cross-coupled architecture
by
Pandey, Abhishek
, Vishwanathan, Vedam
, Nath, Vijay
, Chakraborty, Subhra
, Prasad, Deepak
in
Electronics and Microelectronics
/ Engineering
/ Instrumentation
/ Mechanical Engineering
/ Nanotechnology
/ Technical Paper
2018
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Do you wish to request the book?
Linearity improvement of gain enhanced op-amp using cross-coupled architecture
by
Pandey, Abhishek
, Vishwanathan, Vedam
, Nath, Vijay
, Chakraborty, Subhra
, Prasad, Deepak
in
Electronics and Microelectronics
/ Engineering
/ Instrumentation
/ Mechanical Engineering
/ Nanotechnology
/ Technical Paper
2018
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Linearity improvement of gain enhanced op-amp using cross-coupled architecture
Journal Article
Linearity improvement of gain enhanced op-amp using cross-coupled architecture
2018
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Overview
A novel design structure for high gain linearized operational amplifier using cross coupled differential pair is presented in the current article. This proposed circuit exhibits an improved linearity along with the improved high gain. Cross coupled differential amplifier along with positive feedback has been explicated here for linearity improvement and gain enhancement respectively. An intermediate stage has also been introduced to generate the difference signal as the use of positive feedback in conventional differential amplifier leads to unbalance. Utility of all the parameters like less supply voltage, low power consumption, least possible inaccuracy have been considered while designing. A complete analysis of the circuit is done and described in the present paper which demonstrates how the targeted results are achieved. Circuit performance in the presence of parasitic has also been analyzed. On the other hand, Monte Carlo analysis and harmonic distortion analysis at variable supply voltage and different frequency have also been done. The proposed circuit is implemented in Cadence virtuoso analog and digital design environment using 0.18 μm CMOS technology and analyzed with the assistance of tools from Mentor Graphics. The proposed circuit resides in an active area of 25.96 μm × 27.14 μm and guzzles power of 221 μW. A gain of 124 dB, 307 MHz unity gain bandwidth and a phase margin of 69° have been reported. On the other hand, at 1 V along with 1 kHz frequency, − 74.7 dB distortion has been observed with total harmonic distortion analysis. The high bandwidth reported in the analysis allows the proposed circuit to work for high speed applications whereas high gain makes the circuit applicable in almost every field. The active area of pad-limited chip is found to be 0.96 mm
2
.
Publisher
Springer Berlin Heidelberg
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