Asset Details
Do you wish to reserve the book?
RF and linearity parameters analysis of 20 nm gate-all-around gate-stacked junction-less accumulation mode MOSFET for low power circuit applications
Hey, we have placed the reservation for you!
By the way, why not check out events that you can attend while you pick your title.
Oops! Something went wrong.
Looks like we were not able to place the reservation. Kindly try again later.
Are you sure you want to remove the book from the shelf?
RF and linearity parameters analysis of 20 nm gate-all-around gate-stacked junction-less accumulation mode MOSFET for low power circuit applications
Do you wish to request the book?
RF and linearity parameters analysis of 20 nm gate-all-around gate-stacked junction-less accumulation mode MOSFET for low power circuit applications
Please be aware that the book you have requested cannot be checked out. If you would like to checkout this book, you can reserve another copy
We have requested the book for you!
Your request is successful and it will be processed during the Library working hours. Please check the status of your request in My Requests.
Oops! Something went wrong.
Looks like we were not able to place your request. Kindly try again later.
Journal Article
RF and linearity parameters analysis of 20 nm gate-all-around gate-stacked junction-less accumulation mode MOSFET for low power circuit applications
2024
Overview
For low-power circuit applications, the performance of the circuit is significantly influenced by the MOSFET's analog/RF and non-linearity properties. Gate-all-around junction-less accumulation mode MOSFETs (JAM) are now the perfect choice for low-power circuit applications. In the present work, the gate-stack engineering method is used for gate-all-around junction-less accumulation mode MOSFET (GSJAM) to improve the analog/RF characteristics. The analog/RF and linearity parameter analyses are numerically performed for a 20 nm channel length gate-all-around gate-stacked junction-less MOSFET using an ATLAS 3D device simulator. The comparative analysis of these analog/RF and linearity parameters is also done. The gate stack engineering shows significant improvements in analog/RF parameters, i.e., trans-conductance (g
m
), output resistance (R
out
), early voltage (V
ea
), intrinsic gain (A
V
), trans-conductance frequency product (TFP), gain frequency product (GFP), trans-conductance generation factor (TGF), gain bandwidth product (GBWP), gain trans-conductance frequency product (GTFP), and cut-off frequency (f
T
). The results of the simulation investigation show that when GSJM is compared to JAM MOSFET, the values of gm, R
out
, V
ea
, and TGF are all 26.37%, 2.24 times, 22.38%, and 20.78% higher, respectively. Also, the gate-stack junction-less MOSFET improves the linearity parameters, i.e., 2nd -order trans-conductance (g
m2
)
,
3rd -order trans-conductance (g
m3
), VIP
2
, VIP
3
, IIP
3
, IMD
3
, and 1-dBCP. When comparing GSJAM to JAM MOSFET, the values of VIP2 are 81.63% higher, VIP3 is 1.77 times higher, IIP3 is 6.72 times higher, and 1-dBCP is twice as high. Further, for analog/RF applications, a 20 nm CMOS common-source voltage amplifier circuit using gate-stake junction-less MOSFET has also been designed for a 20 mV and 1 GHz sinusoidal input signal.
Publisher
Springer Berlin Heidelberg,Springer Nature B.V
