Asset Details
Do you wish to reserve the book?
Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
Hey, we have placed the reservation for you!
By the way, why not check out events that you can attend while you pick your title.
Oops! Something went wrong.
Looks like we were not able to place the reservation. Kindly try again later.
Are you sure you want to remove the book from the shelf?
Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
Do you wish to request the book?
Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
Please be aware that the book you have requested cannot be checked out. If you would like to checkout this book, you can reserve another copy
We have requested the book for you!
Your request is successful and it will be processed during the Library working hours. Please check the status of your request in My Requests.
Oops! Something went wrong.
Looks like we were not able to place your request. Kindly try again later.
Journal Article
Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
2020
Overview
In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.
Publisher
MDPI AG,MDPI
Subject
