Journal Article

Application-oriented cache memory configuration for energy efficiency in multi-cores

Diniz, Pedro C., Cuminato, Lucas A., Delbem, Alexandre C.B., Bonato, Vanderlei, Silva, Bruno de Abreu

2015

Overview

This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data-mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time.

• Publisher: The Institution of Engineering and Technology,John Wiley & Sons, Inc
• Subject: Analogies / application‐oriented cache memory configuration / Architecture / automated technique / Automation / cache storage / Clustering / code similarity / Configurations / Customizing / Data mining / data‐mining tool / Design / Digital techniques / Efficiency / Embedded systems / energy conservation / Energy consumption / energy efficiency / field programmable gate array / Field programmable gate arrays / heterogeneous multicore processor systems / HMP system configuration / homogeneous system / L1 cache memory sizes / LEON3 cores / Microprocessors / multiprocessing systems / power aware computing / Scheduling / Special Issue: Energy Efficient Computing with Adaptive and Heterogeneous Architectures / Specialization