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Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene
Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene
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Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene
Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene

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Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene
Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene
Journal Article

Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene

2020
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Overview
The heterostructures of two-dimensional (2D) and three-dimensional (3D) materials represent one of the focal points of current nanotechnology research and development. From an application perspective, the possibility of a direct integration of active 2D layers with exceptional optoelectronic and mechanical properties into the existing semiconductor manufacturing processes is extremely appealing. However, for this purpose, 2D materials should ideally be grown directly on 3D substrates to avoid the transferring step, which induces damage and contamination of the 2D layer. Alternatively, when such an approach is difficult—as is the case of graphene on noncatalytic substrates such as Si—inverted structures can be created, where the 3D material is deposited onto the 2D substrate. In the present work, we investigated the possibility of using plasma-enhanced chemical vapor deposition (PECVD) to deposit amorphous hydrogenated Si (a-Si:H) onto graphene resting on a catalytic copper foil. The resulting stacks created at different Si deposition temperatures were investigated by the combination of Raman spectroscopy (to quantify the damage and to estimate the change in resistivity of graphene), temperature-dependent dark conductivity, and constant photocurrent measurements (to monitor the changes in the electronic properties of a-Si:H). The results indicate that the optimum is 100 °C deposition temperature, where the graphene still retains most of its properties and the a-Si:H layer presents high-quality, device-ready characteristics.