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Darwin:a neuromorphic hardware co-processor based on Spiking Neural Networks
by
Juncheng SHEN De MA Zonghua GU Ming ZHANG Xiaolei ZHU Xiaoqiang XU Qi XU Yangjing SHEN Gang PAN
in
Artificial neural networks
/ CMOS技术
/ Computer Science
/ Data processing
/ Hardware
/ Information Systems and Communication Service
/ Microprocessors
/ Moo Paper
/ Neuromorphic computing
/ Power management
/ Synapses
/ 人工神经网络
/ 协处理器
/ 应用程序
/ 硬件实现
/ 神经形态
/ 脉冲神经网络
/ 达尔文
2016
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Darwin:a neuromorphic hardware co-processor based on Spiking Neural Networks
by
Juncheng SHEN De MA Zonghua GU Ming ZHANG Xiaolei ZHU Xiaoqiang XU Qi XU Yangjing SHEN Gang PAN
in
Artificial neural networks
/ CMOS技术
/ Computer Science
/ Data processing
/ Hardware
/ Information Systems and Communication Service
/ Microprocessors
/ Moo Paper
/ Neuromorphic computing
/ Power management
/ Synapses
/ 人工神经网络
/ 协处理器
/ 应用程序
/ 硬件实现
/ 神经形态
/ 脉冲神经网络
/ 达尔文
2016
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Darwin:a neuromorphic hardware co-processor based on Spiking Neural Networks
by
Juncheng SHEN De MA Zonghua GU Ming ZHANG Xiaolei ZHU Xiaoqiang XU Qi XU Yangjing SHEN Gang PAN
in
Artificial neural networks
/ CMOS技术
/ Computer Science
/ Data processing
/ Hardware
/ Information Systems and Communication Service
/ Microprocessors
/ Moo Paper
/ Neuromorphic computing
/ Power management
/ Synapses
/ 人工神经网络
/ 协处理器
/ 应用程序
/ 硬件实现
/ 神经形态
/ 脉冲神经网络
/ 达尔文
2016
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Darwin:a neuromorphic hardware co-processor based on Spiking Neural Networks
Journal Article
Darwin:a neuromorphic hardware co-processor based on Spiking Neural Networks
2016
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Overview
Broadly speaking, the goal of neuromorphic engineering is to build computer systems that mimic the brain. Spiking Neural Network(SNN) is a type of biologically-inspired neural networks that perform information processing based on discrete-time spikes, different from traditional Artificial Neural Network(ANN).Hardware implementation of SNNs is necessary for achieving high-performance and low-power. We present the Darwin Neural Processing Unit(NPU), a neuromorphic hardware co-processor based on SNN implemented with digitallogic, supporting a maximum of 2048 neurons, 20482= 4194304 synapses, and 15 possible synaptic delays.The Darwin NPU was fabricated by standard 180 nm CMOS technology with an area size of 5 × 5 mm2and70 MHz clock frequency at the worst case. It consumes 0.84 m W/MHz with 1.8 V power supply for typical applications. Two prototype applications are used to demonstrate the performance and efficiency of the hardware implementation.
Publisher
Science China Press,Springer Nature B.V
Subject
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