Journal Article

Spatial‐Wavelength Multiplexing Error‐Controlled Photonic Analog Computing System

Yu, Shaohua, Zhang, Shicheng, Xiao, Xi, Huang, Shanguo, Xu, Xiaochuan, Cao, Zizheng, Guo, Bingli, Zhu, Tao, Zhu, Bowen, Wu, Xianchen, Pi, Yazhi, Yan, Jie, Wang, Lei, Li, Keren, Xue, Xuwei, Chen, Daigao

2026

Overview

In the “post‐Moore era,” the growing challenges in traditional digital computing have driven renewed interest in analog computing. Photonic analog computing has emerged as an effective paradigm for overcoming the fundamental bottlenecks that constrain conventional analog accelerators, especially suited for high‐speed signal processing and next‐generation 5G/6G RF systems. However, existing photonic analog computing frameworks lack the flexibility required to accommodate diverse application scenarios. To address these challenges, a novel silicon photonic chip is proposed in this paper that leverages fully optical analog computation. This system features multichannel architectures to enable spatial multiplexing, a parallel array of four reconfigurable microring resonators performs wavelength division multiplexed differentiation computing. In addition, an FPGA‐based error correction algorithm is developed to monitor processing operations in real time, ensuring the fidelity of computational results. Experimental demonstrations show the system's capability to solve ordinary differential equations and its applications in signal generation, coherent fiber communications, microwave photonics, and image feature detection. Taking into account the spectral utilization efficiency across the entire C‐band, the theoretical on‐chip processing capacity of single unit is evaluated to reach up to 2.725 tera operations per second, providing a novel hardware framework and innovative directions for photonic analog computing. A novel photonic integrated circuit prototype implementing the concept of general‐purpose analog computing and demonstrate its capability in radio frequency applications. The chip features a multichannel architecture and performs fully optical analog computation with frequency‐domain parallel processing. An FPGA‐based error‐correction algorithm aims to eliminate thermally induced drift in the MRR core unit, and ensures the reliability of the processing operations and results.

• Publisher: John Wiley & Sons, Inc,Wiley
• Subject: Integrated circuits / microwave photonics / optical analog computing / Ordinary differential equations / Photonics / reliable computing / Semiconductors / Signal processing / silicon photonic chip