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DESIGNING AN ASYNCHRONOUS FIFO USING VERILOG
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Journal Article
DESIGNING AN ASYNCHRONOUS FIFO USING VERILOG
2022
Overview
The First-In, First-Out (FIFO) method is used to manage computer work requests that originate from stacks or queues, assuring that the request with the earliest arrival time receives processing priority. Using the First-In, First-Out (FIFO) logic, data from one clock domain is transmitted to other clock domains upon request. This task is accomplished in the domain of hardware by a collection of flip-flops or read/write memory components. A more efficient method for constructing a First-In-First-Out (FIFO) system is to compare write and read pointers that are generated in separate clock zones and not simultaneously. The method of comparing pointers in an asynchronous FIFO is used to reduce the number of synchronization flip-flops required to construct the FIFO. In order to effectively construct and evaluate the design using this methodology, it is necessary to employ additional methodologies, as outlined in this academic article. Utilizing mixed binary/gray counters that leverage the inherent binary ripple carry logic is one method employed by this design to improve the efficacy of the First-In-First-Out (FIFO) process.
Publisher
NeuroQuantology
Subject
