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The First-In, First-Out (FIFO) method is used to manage computer work requests that originate from stacks or queues, assuring that the request with the earliest arrival time receives processing priority. Using the First-In, First-Out (FIFO) logic, data from one clock domain is transmitted to other clock domains upon request. This task is accomplished in the domain of hardware by a collection of flip-flops or read/write memory components. A more efficient method for constructing a First-In-First-Out (FIFO) system is to compare write and read pointers that are generated in separate clock zones and not simultaneously. The method of comparing pointers in an asynchronous FIFO is used to reduce the number of synchronization flip-flops required to construct the FIFO. In order to effectively construct and evaluate the design using this methodology, it is necessary to employ additional methodologies, as outlined in this academic article. Utilizing mixed binary/gray counters that leverage the inherent binary ripple carry logic is one method employed by this design to improve the efficacy of the First-In-First-Out (FIFO) process.

A novel power-efficient explicit-pulsed dual-edge triggered flip-flop (SEDNIFF) is proposed. The proposed SEDNIFF puts the latch node inside its structure, which not only simplifies the latch structure but also strengthens the robustness of the output signal. Based on the TSMC0.18 mm technology, the post-layout simulation results show that the proposed flip-flop gains an improvement of up to 17.9 and 23.5% in terms of total average power and power-delay product, respectively, as compared with its counterparts. [PUBLICATION ABSTRACT]

This paper reviews recent advancements in all-optical memory components, particularly focusing on various types of all-optical flip-flops (FFs) based on photonic crystal (PC) structures proposed in recent years. PCs, with their unique optical properties and engineered structures, including photonic bandgap control, enhanced light–matter interaction, and compact size, make them especially suitable for optical FFs. The study explores three key materials, silicon, chalcogenide glass, and gallium arsenide, known for their high refractive index contrast, compact size, hybrid integration capability, and easy fabrication processes. Furthermore, these materials exhibit excellent compatibility with different technologies like CMOS and fiber optics, enhancing their versatility in various applications. The structures proposed in the research leverage mechanisms such as waveguides, ring resonators, scattering rods, coupling rods, edge rods, switches, resonant cavities, and multi-mode interference. The paper delves into crucial properties and parameters of all-optical FFs, including response time, contrast ratio, and operating wavelength. Optical FFs possess significant advantages, such as high speed, low power consumption, and potential for integration, making them a promising technology for advancing optical computing and optical memory systems.

This study presents an innovative single-layered toggle flip-flop with highly polarized output designed specifically for Quantum-dot Cellular Automata (QCA), a cutting-edge nanocomputing approach. Building on the capabilities of this advanced flip-flop, a two-bit asynchronous down (ripple) counter was developed using QCADesigner 2.0.3, all within the QCA framework. The counter exhibits exceptional scalability and reliability, addressing key challenges in QCA circuit design. Energy efficiency and cost-effectiveness are standout features of the design, with a 53% improvement in energy efficiency and a 38% reduction in QCA-specific cost, as verified by QCADesigner-E 2.2 simulations. Furthermore, the physical stability of the proposed circuit was thoroughly examined through kink energy calculations, highlighting its robustness. These optimizations were achieved by avoiding complex crossovers and leveraging the benefits of the enhanced flip-flop architecture. The results underscore the significant potential of QCA in improving digital circuit performance, paving the way for more efficient, scalable, and cost-effective nanoelectronic designs and pushing the boundaries of next-generation nanocomputing solutions.

Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor–capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1–5 GHz frequency, compared to conventional primary–secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power savings and 6.5× reduced skew while using the proposed pulsed resonant flip-flop and saves 64% power and 12.7× reduced skew while using the proposed resonant true single-phase clock (TSPC) flip-flop.

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

Switching-contrast enhancement of over 28 dB for all-optical flip-flop (AOFF) operation of a Fabry–Perót semiconductor optical amplifier (SOA) is experimentally demonstrated. Although the two stable flip-flop states of such a device are typically distinguished by their optical power, it is demonstrated that each stable state can also exhibit a unique state of polarisation (SOP). This bistable polarisation rotation (BPR) is leveraged to achieve extreme contrast enhancement by aligning the AOFF reset-state SOP to the blocking axis of a linear polariser, producing a contrast of 36.6 dB. This contrast-enhancement technique is applicable to other AOFFs based on resonant-type SOAs (RT-SOAs) and Kerr-nonlinear media, substantially improving their applicability to advanced photonic-switching applications.

We report a detailed spectro-temporal analysis of the black hole low mass X-ray binary 4U 1543−475 during its 2021 outburst using the data from the Large Area X-ray Proportional Counter and the Soft X-ray Telescope instruments on board AstroSat . We studied the energy and frequency dependency of the source variability to probe the origin of the disc/coronal fluctuations. Following the state transition (from soft to intermediate state), the emergence of a band-limited noise component is observed along with the power law noise when the disk is recovering from a sudden decrease in the inner disk radius. A possible correlation between the low-frequency root mean square (RMS) variability amplitude and the covering fraction of the non-thermal component is detected. During the final AstroSat observation, a flip-flop phenomenon is reported, where rapid variation in RMS occurs in concurrence with sudden flux transition. An indication of the evolution of inner disk temperature along with a significant change in thermal flux was observed during the flip-flop phase, arguing for a disk instability-driven origin for this phenomenon. Our results suggest that the long-term variability evolution is primarily affected by the coronal changes, whereas the disk behavior governs the short-term variability evolution.

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.

In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS, occurs serious challenges such as higher leakage currents and higher static power consumption have been raised in high-performance circuits. Therefore, to address these issues, we explored carbon nanotube field effect transistors (CNTFETs) with multi-valued logic (MVL). In this paper, we designed an energy-efficient Pulse triggered Ternary Flip Flops (P-TFF) such as Data Close to Output (P-DCO-TFF), Signal Feed Through (P-SFT-TFF), and Delay (P-D-TFF) with pseudo NCFET (N-channel CNTFET) logic. These flip-flops use ternary logic, which is 0, V dd /2, and V dd as logic 0, 1, and 2, respectively. The complete design is done by the stanford 32 nm CNTFETs. The simulations are performed and waveforms are obtained in Cadence Virtuoso Software. We found that the suggested pulse-triggered TFFs performed better than the conventional ternary FF (C-TFF) structure in terms of energy, delay, and power. This simulation result shows 17.8%, 14%, and 47.7% energy reduction in P-SFT-TFF, P-DCO-TFF, and P-D-TFF, respectively, compared with C-TFF structure. Also performed the Monte Carlo Simulations to these proposed TFF designs. The P-D-TFF exhibits very efficient results in terms of delay, energy, and power consumption. This article also simulated the Ternary Universal Shift Register (TUSR) with Proposed P-D-TFF.