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With the development of high-density integrated chips, low-k dielectric materials are used in the back end of line (BEOL) to reduce signal delay. However, due to the application of fine-pitch packages with high-hardness copper pillars, BEOL is susceptible to chip package interaction (CPI), which leads to reliability issues such as the delamination of interlayer dielectric (ILD) layers. In order to improve package reliability, the effect of CPI at multi-scale needs to be explored in terms of package integration. In this paper, the stress of BEOL in the flip-chip chip-scale packaging (FCCSP) model during thermal cycling is investigated by using the finite-element-based sub-model approach. A three-dimensional (3D) multi-level finite element model is established based on the FCCSP. The wiring layers were treated by the equivalent homogenization method to ensure high prediction accuracy. The stress distribution of the BEOL around the critical bump was analyzed. The cracking risk of the interface layer of the BEOL was assessed by pre-cracking at a dangerous location. In addition, the effects of the epoxy molding compound (EMC) thickness, polyimide (PI) opening, and coefficient of thermal expansion (CTE) of the underfill on cracking were investigated. The simulation results show that the first principal stress of BEOL is higher at high-temperature moments than at low-temperature moments, and mainly concentrated near the PI opening. Compared with the oxide layer, the low-k layer has a higher risk of cracking. A smaller EMC thickness, lower CTE of the underfill, and larger PI opening help to reduce the risk of cracking in the BEOL.

Shows how the concepts of vectorization and design masks can be used to help the designer in comparing different designs and making the right choices. The book addresses series and parallel multicell conversion directly, and the concepts can be generalized to describe other topologies.

In this paper, we explore the use of chip-scale blown glass microbubble structures for MEMS packaging applications. Specifically, we demonstrate the efficacy of this method of packaging for the improvement of the lifetime of a ferrofluid-based magnetoviscous magnetometer. We have previously reported on the novel concept of a ferrofluid based magnetometer in which the viscoelastic response of a ferrofluid interfacial layer on a high frequency shear wave quartz resonator is sensitively monitored as a function of applied magnetic field. The quantification of the magnetic field is accomplished by monitoring the at-resonance admittance characteristics of the ferrofluid-loaded resonator. While the proof-of-concept measurements of the device have been successfully made, under open conditions, the evaporation of the carrier fluid of the ferrofluid continuously changes its viscoelastic properties and compromises the longevity of the magnetometer. To prevent the evaporation of the ferrofluid, here, we seal the ferrofluid on top of the micromachined quartz resonator within a blown glass hemispherical microbubble attached to it using epoxy. The magnetometer design used a bowtie-shaped thin film Metglas (Fe85B5Si10) magnetic flux concentrator on the resonator chip. A four-times smaller noise equivalent, a magnetic field of 600 nT/√Hz at 0.5 Hz was obtained for the magnetometer using the Metglas flux concentrator. The ferrofluid-based magnetometer is capable of sensing magnetic fields up to a modulation frequency of 40 Hz. Compared with the unsealed ferrofluid device, the lifetime of the glass microbubble integrated chip packaged device improved significantly from only a few hours to over 50 days and continued.

Emerging trends like the Internet of Things require an increasing number of different sensors, actuators and electronic devices. To enable new applications, such as wearables and electronic skins, flexible sensor technologies are required. However, established technologies for the fabrication of sensors and actuators, as well as the related packaging, are based on rigid substrates, i.e., silicon wafer substrates and printed circuit boards (PCB). Moreover, most of the flexible substrates investigated until now are not compatible with the aforementioned fabrication technologies on wafers due to their lack of chemical inertness and handling issues. In this presented paper, we demonstrate a conceptually new approach to transfer structures, dies, and electronic components to a flexible substrate by lift-off. The structures to be transferred, including the related electrical contacts and packaging, are fabricated on a rigid carrier substrate, coated with the flexible substrate and finally lifted off from the carrier. The benefits of this approach are the combined advantages of using established semiconductor and microsystem fabrication technologies as well as packaging technologies, such as high precision and miniaturization, as well as a variety of available materials and processes together with those of flexible substrates, such as a geometry adaptivity, lightweight structures and low costs.

Purpose This paper aims to assess precise correlations between intermetallic compounds (IMCs) microstructure evolutions and the reliability of micro-joints with a Cu/SAC305solder/Ni structure using thermal shock (TS) tests. Design/methodology/approach This paper uses 200-µm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 60 µm, assembled on substrates with copper (Cu) pads. After assembly, the samples were subjected to air-to-air thermal shock testing from 55 to 125 per cent. The transfer time was less than 5 s, and the dwell time at each temperature extreme was 15 min. To investigate the microstructure evolution and crack growth, two samples were removed from the thermal shock chamber at 0, 400, 1,200, 2,000, 5,800 and 7,000 cycles. Findings The results showed that one (Cu, Ni)6Sn5/(Ni, Cu)3Sn4 dual-layer structure formed at the Ni pad interface of chip side dominates the micro-joints failure. This is because substantial (Ni, Cu)3Sn4 grain boundaries provide a preferential pathway for the catastrophic crack growth. Other IMCs microstructure evolutions that cause the prevalent joints failure as previously reported, i.e. thickened interfacial (Cu, Ni)6Sn5 and Ni3P layer, and coarsened IMCs inside the solder matrix, only contributed to the occurrence of fine cracks. Moreover, the typical interfacial IMCs spalling triggered by thermally induced stress did not take place in this study, showing a positive impact in the micro-joint reliability. Originality/value As sustained trends toward multi-functionality and miniaturization of microelectronic devices, the joints size is required to be constantly scaled down in advanced packages. This arises a fact that the reliability of small-size joints is more sensitive to the IMCs because of their high volume proportion and greatly complicated microstructure evolutions. This paper evaluated precise correlations between IMCs microstructure evolutions and the reliability of micro-joints with a Cu/SAC305solder/Ni structure using TS tests. It found that one (Cu, Ni)6Sn5/(Ni, Cu)3Sn4 dual-layer structure formed at the Ni pad interface dominate the micro-joints failure, whereas other IMCs microstructure evolutions that cause the prevalent joints failure exhibited nearly negligible effects.

<p><b>Examines the advantages of Embedded and FO&#45;WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges</b> <p><i>Embedded and fan&#45;out wafer level packaging</i> &#40;FO&#45;WLP&#41; <i>technologies</i> have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. <p>Filled with contributions from some of the field&#39;s leading experts,<i>??Advances in Embedded and Fan&#45;Out Wafer Level Packaging Technologies</i>??begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip&#45;first FO&#45;WLP, chip&#45;last FO&#45;WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text: <ul> <li>Discusses specific company standards and their development results</li> <li>Relates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging</li> </ul> <p><i>Advances in Embedded and Fan&#45;Out Wafer Level Packaging Technologie</i>s??will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.

The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this work, we present the first comprehensive evaluation of NoC susceptibility to PV effects, and we propose an array of architectural improvements in the form of a new router design-called SturdiSwitch-to increase resiliency to these effects. Through extensive reengineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.

Purpose – The processing techniques and materials utilized in the fabrication of a two-terminal electrostatically actuated micro-electro-mechanical cantilever-arrayed device used for radio frequency tuning applications are presented in this work. The paper aims to discuss these issues. Design/methodology/approach – The process, which is based on silicon surface micromachining, uses spin-coated photoresist as the sacrificial layer underneath the electroplated gold structural material and an insulating layer of silicon dioxide, deposited using plasma enhanced chemical vapour deposition (PECVD), to avoid a short circuit between the cantilever and the bottom electrode in a total of six major fabrication steps. These included the PECVD of the silicon dioxide insulating layer, optical lithography to transfer photomask layer patterns, vacuum evaporation to deposit thin films of titanium (Ti) and gold (Au), electroplating of Au, the dry release of the cantilever beam arrays, and finally the wafer dicing to split the different micro devices. These process steps were each sub-detailed to give a total of 14 micro-fabrication processes. Findings – Scanning electron microscope images taken on the final fabricated device that was dry released using oxygen plasma ashing to avoid stiction showed 12 freely suspended micro-cantilevered beams suspended with an average electrostatic gap of 2.29±0.17 μm above a 4,934±3 Å thick silicon dioxide layer. Preliminary dimensional measurements on the fabricated devices revealed that the cantilevers were at least 52.06±1.93 μm wide with lengths varying from 377.97±0.01 to 1,491.89±0.01 μm and were at least 2.21±0.05 μm thick. Originality/value – The cantilever beams used in this work were manufactured using electroplated gold, and photoresist was used as a sacrificial layer underneath the beams. Plasma ashing was used to release the beams. The beams were anchored to a central electrode and each beam was designed with varying length.

The evolution of IC manufacturing technology has led to a decrease in feature size on the silicon die from around 2m nowadays down to 0.18m, and in the near future down to 0.13m. This implies a simultaneous decrease in the distance of the individual contact pads pitch, decreasing from a moderate 0.5mm to nowadays 0.1mm or even 0.07mm for leading edge ICs. The near future will not allow this trend to continue. Instead of peripheral contacts, several rows of contacts or even use of the entire die area to accommodate the contacts will allow the numbers of IOs to increase to the required value. Following the roadmap of electronic devices the PCB has its design continuously changed. Accordingly we need today PCBs with high density interconnects, realized by sequential buildup technology SBU including microvias. We see at the end of the next decade that the semiconductor technology will be introduced at the PCB level. At this time we are also able to transfer the chip design into the PCB directly. This dependence of the development from chip and PCBtechnology is the subject of the paper.