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Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
by
RamPrasad, M. V. S.
, Teja, Chelluri Ravi
, Dinesh, Gundala
, Yeshaswila, Eegala Yamini
, Yamani, Sudha Vani
, Lokesh, Botta
in
Carbon
/ Carbon nanotubes
/ Circuits
/ Circuits and Systems
/ CMOS
/ Delay
/ Design
/ Electrical Engineering
/ Electronic systems
/ Energy consumption
/ Energy efficiency
/ Engineering
/ Field effect transistors
/ Flip-flops
/ Leakage current
/ Monte Carlo simulation
/ Multivalued logic
/ Power consumption
/ Power management
/ Semiconductor devices
/ Shift registers
/ Signal,Image and Speech Processing
/ Transistors
/ Waveforms
2024
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Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
by
RamPrasad, M. V. S.
, Teja, Chelluri Ravi
, Dinesh, Gundala
, Yeshaswila, Eegala Yamini
, Yamani, Sudha Vani
, Lokesh, Botta
in
Carbon
/ Carbon nanotubes
/ Circuits
/ Circuits and Systems
/ CMOS
/ Delay
/ Design
/ Electrical Engineering
/ Electronic systems
/ Energy consumption
/ Energy efficiency
/ Engineering
/ Field effect transistors
/ Flip-flops
/ Leakage current
/ Monte Carlo simulation
/ Multivalued logic
/ Power consumption
/ Power management
/ Semiconductor devices
/ Shift registers
/ Signal,Image and Speech Processing
/ Transistors
/ Waveforms
2024
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Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
by
RamPrasad, M. V. S.
, Teja, Chelluri Ravi
, Dinesh, Gundala
, Yeshaswila, Eegala Yamini
, Yamani, Sudha Vani
, Lokesh, Botta
in
Carbon
/ Carbon nanotubes
/ Circuits
/ Circuits and Systems
/ CMOS
/ Delay
/ Design
/ Electrical Engineering
/ Electronic systems
/ Energy consumption
/ Energy efficiency
/ Engineering
/ Field effect transistors
/ Flip-flops
/ Leakage current
/ Monte Carlo simulation
/ Multivalued logic
/ Power consumption
/ Power management
/ Semiconductor devices
/ Shift registers
/ Signal,Image and Speech Processing
/ Transistors
/ Waveforms
2024
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Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
Journal Article
Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
2024
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Overview
In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS, occurs serious challenges such as higher leakage currents and higher static power consumption have been raised in high-performance circuits. Therefore, to address these issues, we explored carbon nanotube field effect transistors (CNTFETs) with multi-valued logic (MVL). In this paper, we designed an energy-efficient Pulse triggered Ternary Flip Flops (P-TFF) such as Data Close to Output (P-DCO-TFF), Signal Feed Through (P-SFT-TFF), and Delay (P-D-TFF) with pseudo NCFET (N-channel CNTFET) logic. These flip-flops use ternary logic, which is 0, V
dd
/2, and V
dd
as logic 0, 1, and 2, respectively. The complete design is done by the stanford 32 nm CNTFETs. The simulations are performed and waveforms are obtained in Cadence Virtuoso Software. We found that the suggested pulse-triggered TFFs performed better than the conventional ternary FF (C-TFF) structure in terms of energy, delay, and power. This simulation result shows 17.8%, 14%, and 47.7% energy reduction in P-SFT-TFF, P-DCO-TFF, and P-D-TFF, respectively, compared with C-TFF structure. Also performed the Monte Carlo Simulations to these proposed TFF designs. The P-D-TFF exhibits very efficient results in terms of delay, energy, and power consumption. This article also simulated the Ternary Universal Shift Register (TUSR) with Proposed P-D-TFF.
Publisher
Springer US,Springer Nature B.V
Subject
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