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This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.

Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness. Article Highlights Hybrid full adders offer better performance than single logic full adders Many existing full adder cells are not scalable Conventional Mirror CMOS full adder offers better performance than many recent full adders in wide adder structure

Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.

This paper introduces a new low-power pass transistor logic adder (PTLA) design utilizing 22 nm GNRFET (Graphene Nano Ribbon Field Effect Transistor) technology to enhance computing performance. The PTLA is designed with pass transistor logic that helps in optimization of transistor count. By effectively integrating PTLA with a low-power trimode technique, the proposed design optimizes key metrics such as power consumption, delay, and area. The innovative use of graphene based GNRFET ensures high carrier mobility and temperature resilience, while the trimode technique dynamically manages operational states for improved energy efficiency. The performance of two distinct configurations, 24T PTLA and 21T PTLA, has been evaluated under varying temperature and voltage conditions. Process voltage temperature (PVT) and Monte Carlo analysis validate the proposed circuits’ adaptability and reliability, showcasing substantial improvement in power-delay product (PDP) and leakage current. These advancements establish the designs as ideal candidates for AI-enabled devices and edge computing applications, where low power and high speed are critical parameters. Extensive Synopsys HSPICE simulations have been employed for performance optimization, demonstrating the robustness of the designs for next generation digital computing technologies. The 24T PTLA structure reduces the power by 99.9% and PDP by 99.5% compared to conventional CMOS, hybrid and transmission gate logic, which proves the highly energy-efficient nature of the circuit. The 21T PTLA design enhances delay stability by 99.6% and reduces leakage current by 99.8%, which ensures dependable performance under diversified conditions.

The impact of the work function modulation (WFM) in sub-20nm strained silicon channel double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power arithmetic circuit applications. A 14nm double gate junctionless transistor (DGJLT) followed by formation of strained channel and WFM in metal gate is designed on sentaurus TCAD, where 2-D mixed mode simulation at supply voltage (V D D ) = 0.8V is performed to configure a hybrid full adder (HFA). From the analyses, the WFM based HFA is found to be superior by providing the least power, delay and PDP. The variability of HFAs is also tested as a function of the physical parameters like V D D , load capacitor, and temperature.

Digital multipliers are the core components of digital computers, and improving the speed of transistor electronic computers during computation has almost reached its limit, with high power consumption. In this paper, we proposed an electro-optic hybrid multidigit digital multiplier based on SPP technology, which has the advantages of high speed and low power consumption in optical logic, as well as flexible electrical operation and easy storage. The electro-optic hybrid digital multiplier mainly consists of an electrical AND logic gate, an electro-optic hybrid half adder, and an electro-optic hybrid full adder. The optical logic unit is controlled by activated ITO materials to achieve optical-domain operations, and then the multiplication calculation results are converted into electrical signals through photoelectric conversion. The experimental results show that when the scale is 64 × 64 bits, compared with transistor digital multiplication, the energy consumption is reduced by 48.8%; the speed is increased by a factor of 28; and the volume of the electro-optic hybrid digital multiplier device is larger than that of the transistor multiplier, saving 59.9% of the area. For optical transmission loss, a single adder outputs 0.31 dB at different device scales, while the carry output continuously increases with device scale. At scales of 8 × 8 bits, 16 × 16 bits, and 64 × 64 bits, the insertion losses at the sum output ports are 1.03 dB/μm and 1.87 dB/μm, respectively.

A FinFET-based 8-bit low-power arithmetic and logic unit (ALU) with full-swing 9-transistor GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating-aware energy-efficient ALU is proposed using this adder and signal gating circuit. An adaptive signal gating is applied according to the current ALU operation based on the particular operation corresponding control word. The input signals to the other blocks are gated such that the proposed intelligent signal gating scheme customizes the overall power utilization of the proposed ALU. The proposed ALU has been implemented using 20 nm FinFET PTM models. The total power consumption of the conventional FinFET ALU to execute all eight operations is 619.55 µW, whereas the proposed ALU consumes 225.53 µW only. The average power consumption of the traditional FinFET ALU is 77.44 µW per operation, while the proposed low-power ALU needs 28.19 µW only. The maximum amount of total and average power that the proposed scheme can optimize is 63.59%.

The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed full adders, using metrics such as power dissipation, propagation delay and power delay product. Comparative performance shows that the proposed 1-bit full adder shows average improvement in terms of power dissipation (31.62 nW and 20.84 nW) and average delay (5.07ns and 11.41ns) over the existing 1-bit hybrid and cell 3 full adder circuit.

This paper presents a new method for implementing an efficient digital down converter (DDC) using a field-programmable gate array (FPGA) for software-defined radio standards. The DDC consists of a pipeline coordinate rotation digital computer (CORDIC) rotator to produce a complex waveform, followed by a cascade of multi-stage cascaded integrator comb (CIC) filter and a polyphase transposed finite impulse response (PTFIR) filter to reduce large sample rates with lowpass filtering. The canonical signed-digit encoding in the CORDIC architecture reduces many adders and shifters. The CIC filter works with a new polynomial function that reduces passband droop by 34.29% and stopband ripple by 41.35% when compared with the traditional approach. The proposed PTFIR filter considerably reduces delay units. Again, the adder is the basic functional unit of the DDC structure. In this brief, each component of the DDC is examined with hybrid parallel prefix adders. The presented HPPA utilizes less critical path delay and less area when compared to conventional structures. The design has been simulated in the Xilinx Vivado 2022.1, which implements the FPGA Kintex-7 device. According to comparison results, the proposed DDC reduces approximately 30.51% of the area-delay product and 29.32% of the power-delay product associated with the best design. A verification test certifies the functionality of the prototype architecture.

This research article introduces an innovative 1-bit full adder design, leveraging grounded keeper circuitry. To implement full adder, keeper based XOR-XNOR cell -based design approach is used. Achieving full swing output voltage is one of the critical challenges in the designing of full adder. In this paper 8-T XOR-XNOR cell is proposed and simulated using HSPICE software at 90 nm technology node. The introduction of keeper circuit, which decreases propagation delay and offer full output voltage swing, is the primary focus of this research. Furthermore, this work puts forth an original design for a voltage-resilient ultra high-speed low-power keeper-based 1-bit full adder (UHSLPFA). Our research delves into a comprehensive comparison of various full adder designs, focusing on power dissipation (PWR), propagation delay (tp), and power-delay product (PDP). Notably, our proposed 20-T full adder design boasts notably reduced propagation delay and power consumption when compared to the existing counterparts. The envisioned application scope for this voltage-resilient ultra-high-speed-low-power keeper-based 1-bit full adder extends to the development of arithmetic logic units, multipliers, calculators, and graphical processing units. To gauge its voltage resilience, our proposed UHSLPFA is subjected to simulation across a range of supply voltages, from 0.6 to 1.5 V. This evaluation uncovers variations in PWR, tp, and PDP, showcasing the superior resilience of our design compared to contemporary state-of-the-art alternatives. The performance of the proposed full adder is also evaluated in 4-bit ripple carry adder.