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Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
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Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
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Paper
Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
2021
Overview
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, critical currents of interlayer vias are presented. Comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.
Publisher
Cornell University Library, arXiv.org
