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High-Voltage Electrostatic Discharge/Electrical Overstress Co-Protection Implementing Gradual-Triggered SCR and MOS-Stacked Configuration
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High-Voltage Electrostatic Discharge/Electrical Overstress Co-Protection Implementing Gradual-Triggered SCR and MOS-Stacked Configuration
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Journal Article
High-Voltage Electrostatic Discharge/Electrical Overstress Co-Protection Implementing Gradual-Triggered SCR and MOS-Stacked Configuration
2025
Overview
This paper proposes a monolithic electrostatic discharge/electrical overstress (ESD/EOS) co-protection device featuring gradual triggering by silicon-controlled rectifier (SCR) and metal–oxide semiconductor (MOS) structures, demonstrating enhanced voltage clamping and current-conducting capabilities. Compared with conventional PMOS-triggered SCR (PMOS-SCR) for ESD protection, the proposed dual-PMOS-triggered SCR (DPMOS-SCR) architecture within a compact area achieves monolithic ESD/EOS protection performance due to the strategic semiconductor structures integration. ESD measurement results show that the snapback voltage of the designed DPMOS-SCR with the width of 170 μm is approximately 2.5 V, the failure current (It2) is up to 4.5 A, and both the simulation and measurement results demonstrate that the designed DPMOS-SCR is helpful for reducing the leakage current and accelerating the response time. By embedding an additional p-type well in the DPMOS-SCR, the optimized DPMOS-SCR (ODPMOS-SCR) presents a higher breakdown voltage, trigger voltage, and holding voltage while keeping a similar It2. The EOS current-conducting ability measured by a surge test system indicates the peak surge current is up to 3.7 A, demonstrating superior monolithic ESD/EOS protection performance. As a result, the designed DPMOS-SCR and ODPMOS-SCR structures achieve high-voltage ESD/EOS co-protection with high efficiency in a small chip area, providing a chip-scale solution for improving the reliability of high-voltage ICs.
Publisher
MDPI AG
