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Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters
Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters
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Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters
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Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters
Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters

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Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters
Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters
Journal Article

Fuzzy Logic PID Controller with Both Coefficient and Error Modifications for Digitally-Controlled DC–DC Switching Converters

2023
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Overview
To improve the transient response performance of digitally-controlled DC–DC switching converters, a fuzzy logic control proportional-integral–differential (FLC–PID) controller with both coefficient and error modifications is presented in this paper. The controller consists of a PID compensator and two fuzzy logic controllers (FLCers): one that adjusts the control coefficients of PID compensator and another that modifies voltage error input to it. These two FLCers have different fuzzy input subsets (FIS), leading to multiple modifications of control coefficients and voltage error for PID compensator. Consequently, the proposed controller results in finer FIS than a conventional FLC–PID controller without significantly increasing the hardware cost. Experimental results demonstrate that it yields a better transient performance in a DC–DC switching converter than does a conventional FLC–PID controller that only modifies the PID control coefficients: the transient performance can be improved by at least 50% and the required hardware resources can be reduced by at least 20%.