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A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration
A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration
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A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration
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A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration
A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration

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A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration
A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration
Journal Article

A Maximum-Clearance Optimization Model with Chaotic Initialization for PCB Component Pin Registration

2026
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Overview
Automatic insertion machines play an important role in the assembly of through-hole electronic components on printed circuit boards (PCBs). However, for irregular multi-pin components, fixed-position registration strategies may fail to recover feasible insertion poses under grasping errors, manufacturing tolerances, and transportation-induced pin perturbations. To address this issue, this paper proposes a maximum-clearance optimization model with chaotic initialization for PCB component pin registration. First, the Graham–Scan algorithm is employed to generate convex polygons to simulate the geometric layout of component pins. Subsequently, random perturbations following two-dimensional normal distributions are introduced to simulate pin deformation caused by manufacturing and transportation processes. Then, a maximum-clearance objective is formulated to determine a feasible insertion pose under bounded translational and rotational adjustments. Finally, the resulting registration model is first evaluated through a solver-level comparison among three general-purpose numerical optimizers—namely, SLSQP, genetic algorithm, and simulated annealing—all applied to the same maximum-clearance formulation. In addition, representative registration baselines are introduced in a supplementary cross-paradigm comparison to clarify the difference between alignment-oriented registration accuracy and clearance-oriented insertion feasibility. Experimental results under an industrially motivated simulation setting show that, when solved by SLSQP, the proposed model achieved a clearance-based surrogate success rate of 98.44% over a complete simulated dataset of 1,400,000 samples, while maintaining an average computation time of 0.0198 s per sample. These results suggest that the proposed method provides computational evidence for the potential usefulness of a clearance-oriented geometric registration framework under simulated PCB insertion conditions motivated by field investigation data from Dalian Rijia Electronics Co., Ltd., rather than direct validation on a fully instrumented production line.