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Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
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Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
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Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET

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Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
Journal Article

Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET

2023
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Overview
FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.