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A scalable universal Ising machine based on interaction-centric storage and compute-in-memory
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A scalable universal Ising machine based on interaction-centric storage and compute-in-memory
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Journal Article
A scalable universal Ising machine based on interaction-centric storage and compute-in-memory
2024
Overview
Ising machines are annealing processors that can solve combinatorial optimization problems via the physical evolution of the corresponding Ising graphs. Such machines are, however, typically restricted to solving problems with certain kinds of graph topology because the spin location and connections are fixed. Here, we report a universal Ising machine that supports arbitrary Ising graph topology with reasonable hardware resources using a coarse-grained compressed sparse row method to compress and store sparse Ising graph adjacency matrices. The approach, which we term interaction-centric storage, is suitable for any kind of Ising graph and reduces the memory scaling cost. We experimentally implement the Ising machine using compute-in-memory hardware based on a 40 nm resistive random-access memory arrays. We use the machine to solve max-cut and graph colouring problems, with the latter showing a 442–1,450 factor improvement in speed and 4.1 × 10
5
–6.0 × 10
5
factor reduction in energy consumption compared to a general-purpose graphics processing unit. We also use our Ising machine to solve a realistic electronic design automation problem—multiple patterning lithography layout decomposition—with 390–65,550 times speedup compared to the integer linear programming algorithm on a typical central processing unit.
An Ising machine that uses a coarse-grained compressed sparse row method to store sparse Ising graph adjacency matrices can be implemented with compute-in-memory hardware based on a resistive random-access memory array to efficiently solve combinatorial optimization problems.
Publisher
Nature Publishing Group UK,Nature Publishing Group
Subject
/ Arrays
/ CMOS
/ CPUs
/ Design
/ Electronic design automation
/ Field programmable gate arrays
/ Graphs
/ Hardware
/ Silicon
/ Topology
