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![Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique](https://www.mbrl.ae/o/mbrl-theme/images/site-assets/generic/no-book-image.png)
Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique
by
Lee, Chang-Chun
, Huang, Pei-Chen
in
Annealing
/ annealing process
/ carrier mobility estimation
/ Design
/ Efficiency
/ Electronic packaging
/ Exact solutions
/ finite element analysis
/ Finite element method
/ Germanium
/ Impact analysis
/ Influence
/ Integrated circuits
/ Interconnections
/ Investigations
/ Mathematical analysis
/ Metal oxide semiconductors
/ MOSFET
/ MOSFETs
/ Performance evaluation
/ Residual stress
/ Semiconductor devices
/ Simulation
/ Transistors
/ TSV
2021
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Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique
by
Lee, Chang-Chun
, Huang, Pei-Chen
in
Annealing
/ annealing process
/ carrier mobility estimation
/ Design
/ Efficiency
/ Electronic packaging
/ Exact solutions
/ finite element analysis
/ Finite element method
/ Germanium
/ Impact analysis
/ Influence
/ Integrated circuits
/ Interconnections
/ Investigations
/ Mathematical analysis
/ Metal oxide semiconductors
/ MOSFET
/ MOSFETs
/ Performance evaluation
/ Residual stress
/ Semiconductor devices
/ Simulation
/ Transistors
/ TSV
2021
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![Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique](https://www.mbrl.ae/o/mbrl-theme/images/site-assets/generic/no-book-image.png)
Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique
by
Lee, Chang-Chun
, Huang, Pei-Chen
in
Annealing
/ annealing process
/ carrier mobility estimation
/ Design
/ Efficiency
/ Electronic packaging
/ Exact solutions
/ finite element analysis
/ Finite element method
/ Germanium
/ Impact analysis
/ Influence
/ Integrated circuits
/ Interconnections
/ Investigations
/ Mathematical analysis
/ Metal oxide semiconductors
/ MOSFET
/ MOSFETs
/ Performance evaluation
/ Residual stress
/ Semiconductor devices
/ Simulation
/ Transistors
/ TSV
2021
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Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique
![Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique](https://syndetics.com/index.aspx?isbn=/mc.gif&issn=1996-1944&client=MBRL&type=mbrl)
Journal Article
Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique
2021
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Overview
Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.
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