Journal Article

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Tao, Quanyang, Li, Yunxin, Liu, Liting, Yang, Xiaokun, Wang, Yiliu, Lu, Zheyi, Kong, Lingan, Chen, Yang, Li, Zhiwei, Duan, Xidong, Hu, Yuanyuan, Liu, Xiao, Liu, Yuan, Ding, Shuimei, Ma, Likuan, Wu, Ruixia, Lu, Donglin, Liao, Lei

2024

Overview

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching 1 – 10 . However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics 11 – 13 , where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers. We develop a low-temperature, damage-free process using van der Waals lamination to integrate multiple circuit tiers into a monolithic three-dimensional device, incorporating unique multi-tier functionality and resolving legacy issues with the layering technology.

• Publisher: Nature Publishing Group UK,Nature Publishing Group
• Subject: 140/133 / 639/166/987 / 639/301/1005/1007 / 639/925/927/1007 / Cold Temperature / Electrical properties / Energy / Equipment Design / Free surfaces / Humanities and Social Sciences / Integration / Laminating / Lamination / Low dimensional semiconductors / Low temperature / multidisciplinary / Plasma etching / Polymers / Polyvinyl alcohol / Science / Science (multidisciplinary) / Semiconductors / Silicon wafers / Substrates / Temperature / Thin bodies / Transistors / Transistors, Electronic / Two dimensional bodies